=_cÏ´¡ 9X4
O–® –}®~–ƒ®„–® –When a value is stored using STF, it is rounded using 'to nearest' rounding to the precision specified in the instruction. (E and P will always store results without requiring rounding.) If some other rounding method is required, this can be done first using a MVF instruction from the register to itself, using the appropriate rounding mode.
LÔK·F·NÑ-¢2
–If an attempt is made to store a trapping NAN value, an exception will occur if the IVO trap is enabled, otherwise the value will be stored as a non-trapping NAN. OFL errors can occur on stores if the number is too large to be converted to the specified format.
MáH³LØ&ä£
‚Examples:
GM¥ ˆB.6 Formats of numbers
h:¦‚
‚–Each of the four precisions has its own representation of legal numbers and special values. These are described in this section.
LÙ68§ ‰Single precision
¡ª ‚Formats of values
z® ‰Double precision
@©± ‚Extended precision
(…´j
j–NB The relative positions of the three parts of the first word had not been finalised as of this writing.
LÎ§µ ‚Format of values
ar¤0
™™™™™ ™™™ Sign Exponent J Mantissa
x@¹¸ ‰Packed decimal
š» ‚Format of values
ÿr¾B
B–Note that when -0 is stored in this format it is converted to +0.
B…¿5e
e–There is a fixed correspondence between the precision of a number expressed in bits, and how many decimal digits that number can represent. Mathematically speaking, an n-bit number can hold n*LOG(2)/LOG(10) decimal digits, or more simply, n*0.3010. Thus the three IEEE floating points types can accurately represent the following number of decimal digits:
-B¢JÔCÆH¹NßšD
–To obtain numbers greater than 1.999999... a positive exponent is used, and to represent numbers smaller than 1.0, a negative exponent is used (meaning that the mantissa is divided by a power of two instead of multiplied). The exact range of numbers depends on the maximum power of two by which the mantissa may be multiplied or divided. This is known as the dynamic range of the representation.
MÛLâLÍDÌIÈ°Á0 0š Type Precision Decimal digits
0^Ã,( š
ššš"š#š Precision Exponent bits Smallest Largest
,…ž,õ
õ–The flags are set if the appropriate condition has arisen, and cleared if not. The masks are set to enable the interrupt, and cleared to disable it. There is an FPU instruction which is used to initialise the status register to a known state.
PØPØNÕ#tÆ¡
¡–'Round to plus infinity' means that the final result is the first number which is greater than the 'exact' result which can be stored in the required precision.
OÖG¦=Ç:i
i–To the programmer, the FPU looks like a cut-down version of the ARM CPU. There are eight general purpose registers, called F0 to F7, a status register and a control register. There is no program counter; the ARM controls all interaction between a co-processor and memory. It is responsible for generating addresses for instruction fetches and data transfers.
D¿JÅG»C›F°=ÈeV
V–The FPU's status register is 32-bits wide, and contains three fields. These are the status flags, the interrupt masks, and a system id field. There are five flags, and each of these represents a specific error condition which can arise during floating point operations. Each flag has a corresponding interrupt mask. When an error condition arises, the FPU checks the state of the interrupt mask for that error. If the interrupt is enabled, a trap is generated, which causes the program to halt. The appropriate status flag is set, so that the trap handler can determine the cause of the error.
PáMÈOÜKÐG´RàOÝ7NË(`
2–– –P#–+–,–P^–f–g–P™–š–›–œ–P»–Ã–Ä–Pã–ä–å–æ– Nearest Appropriately signed INF
To zero Largest representable number of appropriate sign
To +INF Negative overflows go to largest negative number
Positive overflows go to +INF
To -INF Negative overflows go to -INF
Positive overflows go to largest positive number
#;©;®"/(55 Ì%`
–– –P$–,–-–PH–P–Q–Po–p–q–r–P¦–®–¯–Pã–ä–å–æ– Nearest Appropriately signed zero
To zero Appropriately signed zero
To +INF Negative underflows go to -0
Positive underflows go to smallest positive number
To -INF Negative underflows go to smallest negative number
Positive underflows go to +0
$$'*7°=¾!$ÍD ™™P™/™ MNM{cond}{R} ,
MNM{cond}

{R} ,,
%BÎ%Û
Õ®– is the FPU register to hold the result. The standard names for the FPU registers are F0-F7, and assemblers which recognise the FPU instructions allow other names to be assigned, as for the normal ARM registers.
KÔ@ŸE¸;Ï)L ™™™ ™
™™™P™™™™™™"™#™ 0.0 1.0 2.0 3.0
4.0 5.0 0.5 10.0
Þæ¿J`"8 ™™™ ™
™™™
™P%™)™*™3™4™5™PM™Q™R™[™\™]™Pu™y™z™‡™ˆ™P ™¤™¥™¬™™®™¯™PÇ™Ë™Ì™Ù™Ú™Pò™ö™÷™ý™þ™ÿ™™P™™™+™,™PD™H™I™S™T™U™Po™s™t™‚™ƒ™P›™Ÿ™ ™¬™™PÅ™É™Ê™Ú™Pò™ö™÷™™™ ADF add = +
MUF multiply = *
SUF subtract = -
RSF reverse sub. = -
DVF divide = /
RDF reverse div. = /
POW power = ^
RPW reverse power = ^
RMF remainder = REM
FML fast multiply = *
FDV fast divide = /
FRD fast rev. div. = /
POL polar angle = arctan(/)
%’(’(’+’'’+’&’,’+¢,’*’-’0ÂÀ,,
æ–®–®–#®&–The 'fast' operations FML, FDV and FRD are performed in single precision, rather than full working precision used for the other calculations. This means that rounding to any precision will always yield a result which is only as accurate as a single precision number.
JÓJ¼NÞ*þÁ@
®–7®<–@®E–W®f–o®p–‹®Ž–REM , gives the remainder of the division of by . In other words, a REM b = a-b*n, where n is the nearest integer to a/b.
@·@¶_ÂQRT ™™™
™™™
™P™!™"™/™0™PA™E™F™U™V™Pl™p™q™™€™P ™¤™¥™±™²™PÇ™Ë™Ì™Ø™Ù™Pð™ô™õ™™™™P™™™(™)™P=™A™B™G™H™I™J™P_™c™d™k™l™m™n™Pƒ™‡™ˆ™™‘™’™P§™«™¬™´™µ™¶™PË™Ï™Ð™Ú™Û™Ü™Pñ™õ™ö™™™™ MVF move =
MNF move negated = -
ABS absolute value = ABS()
RND integer value = roundToInteger()
SQT square root = SQR()
LOG log base 10 = LOG10()
LGN log base e = LN()
EXP e to a power = e ^
SIN sine = SIN()
COS cosine = COS()
TAN tangent = TAN()
ASN arcsine = ATN()
ACS arccosine = ACS()
ATN arctangent = ATN()
R$Z+‚4Ò'z)Š&r'r"z$z$z$z&z'zÃÉT !™™™6™7™=™F™G™Pj™o™u™v™w™Pš™Ÿ™§™¨™ MUFS F0,F1,#10.0 ;F0=F1*10, single precision,nearest POWDZ F2,F3,F4 ;F2=F3^F4, double precision,zero
SINE F7,F0 ;F7=SIN(F0), extended, to nearest
EXPE F0,#1.0 ;F0='e' as an extended constant
7î3Î0Î/¾ÄN ™™P'™7™ FIX{cond}

{R} ,
FLT{cond}

{R} ,
'R'RÅ`, ™™
™P1™7™=™L™ FIXNES R0,F2 ;Convert F2 to integer in R0 if NE
FLTSZ F1,R0 ;Convert R0 to F1, round to zero
1/Æ, ™
™P™ ™ RFS{cond}
WFS{cond}
ÁÁÇ, ™
™P™ ™ RFC{cond}
WFC{cond}
ÁÁÈ ™™P™™ RFS R4
WFC R0
HHÉ
™™ MNM{cond}

{R} ,
Ê„\ ™™™
™™™P™"™#™3™PB™G™O™P™Q™P`™e™u™v™ CMF compare -
CNF compare negated +
CMFE compare -
CNFE compare negated +
Ë$,
–
®–®–® –Note that if V=1, then N=0 and C=0.
$ßÌÀT &™™
™P4™:™@™A™Pb™c™d™e™f™g™s™@™’™š™ CMFE F0,#0.0 ;See if F0 is 0.0, extended precision
CMFEE F1,F2 ;Compare F1, F2 using extended
;precision with disordered exception
CNFS F3,#1.0 ;Compare single precision F3 with -1
4Ò.¢+Ê3ÊÍF ™
™P#™0™ LDF{cond}

,

STF{cond} ,

#-#-Î›< &™™
™P1™6™<™=™d™e™j™u™ STFP F0,[R0] ;Store F0 in packed format at [R0]
LDFE F0,pi ;Load constant from label 'pi' STFS F1,[R2],#4 ;Store single prec. number, inc. R2
1º4â6ÊÏ;,6ü ššššššššP2š>š?š@šBšCšKšLšNšP[š^š_š`šašbšdšešmšnšpšPƒš‡šˆš‰šŠšŒšššš‘š“šP¦š¹š»š¼š¾š¿šÀšÂšPÎšášãšäšîšðšPšššš!š#šNon-trapping NAN x Maximum x 1xxxxxxxxxxxxx...
Trapping NAN x Maximum x 0
INF s Maximum 0 00000000000000...
Zero s 0 0 00000000000000...
Denormalised number s 0 0
Un-normalised numbr s Not 0/Max 0 xxxxxxxxxxxxxx...
Normalised number s Not 0/Max 1 xxxxxxxxxxxxxx...
2¯)…(¯#¯(~5¯3¯Ð0õÐ šššššššP0š<š=š>š@šAšIšJšPWšZš[š\š]š^š`šašišjšP}šš‚šƒš„š†š‡š‰šŠš‹šPžš±š³š´š¶š·š¸šPÄšÕšÖš×šØšâšNon-trapping NAN x Maximum 1xxxxxxxxxxxxx...
Trapping NAN x Maximum 0
INF s Maximum 00000000000000...
Zero s 0 00000000000000...
Denormalised number s 0
Normalised number s Not 0/Max xxxxxxxxxxxxxx...
0’'h&’!’&a1’Ñ,
™™™™™ ™™ Sign Exponent Mantissa
[Ò 4 ™™™™™™™™™ bit 31 30 e3-e0 d18-d0
hÓ0 ÚÐ ššššššššP0š<š=š>š?šAšCšIšJšP^šašbšcšdšešfšhšjšpšqšP…š‰šŠš‹šŒššš‘š’š—š˜šP¬š²š³š´šµš¶š¸šºšÆšNon-trapping NAN x x &FFFF d18>7, rest non 0
Trapping NAN x x &FFFF d18<=7, rest non 0
INF s x &FFFF &00000000000000...
Zero 0 0 &0000 &00000000000000...
Number s s &0000-&9999 &1-&99999999999...
0¯.¶'¶'¶.¶¿:w
w–At the other end of the spectrum, a complete hardware implementation of the FPU would recognise the whole floating point instruction set, so the unimplemented instruction trap would never be used. The ARM's only involvement in dealing with the instructions would be in the generation of addresses for data transfers and providing or receiving values for register transfers.
HÏIÂD¼KÑLÓ=ÁSÔ
–È«Í–When we say a given floating point representation has n bits of precision, this means that the mantissa part is stored in n bits. The three standard IEEE precisions are 24 bits, 53 bits and 65 bits. These are known as single, double, and extended precision respectively. The mantissa is stored in one fewer bits than the precision implies because numbers are held in normalised form (as in BBC BASIC) and the MSB is an implicit 1. The binary point comes after this.
KÌKÁNÌKÏMàF¹g©'ß
Üª–UFL - Underflow. This occurs when a number becomes too small (i.e. too close to zero) to represent properly in the specified precision. If the error is not trapped, the result is affected by the rounding mode as follows:
HÌRÕE¡ÔQÝÃ r &šP%šPLš Single 24 7.2
Double 53 15.95
Extended 65 19.6
Å<T
T–The mantissa has an imaginary binary point before after its first digit, and the first digit is always a binary 1, never 0. This is known as 'normalised form'. Thus the mantissa stands for a fraction between 1.0 and 1.99999... The exponent provides the power of two by which the mantissa has to be multiplied to obtain the desired value.
MÑMÅKÉGÉ(íÆ)\´ ššš ššš
šššššššššAš#š$š%š(š)š*š+š-š2š3š5š9š@:šCšDšEšHšIšJšKšMšSšTšVš[š Single 8 2-126 2127
Double 11 2-1022 21023
Extended 15 2-16382 216383
jo"tÉ]1(
––F–“–Ù–$–When the FPU performs its calculations, more digits are used than are necessary to store the numbers involved. Calculations are performed in what is called 'full working precision'. This is so that any errors which accumulate due to non-exact representations of fractions do not affect the final result. When a result is presented, the FPU converts the special full working form into a value of the desired precision. The way in which this conversion is performed is called the 'rounding mode' of the calculation, and there are four of them to choose from.
F¸HÄKºKÒMÅKÍNà'î±KÃ
Àª–INX - Inexact. This error occurs whenever a rounded result is obtained which is different from that which would have been calculated if 'infinite' working precision was used. Calculating the sine, cosine or tangent of an angle greater than 10E20 radians causes this error. Also, all OFL errors automatically cause this error, so if the OFL trap is disabled but the INX trap is enabled, an overflow will cause the inexact interrupt to be generated.
HÀLÌKÎJÃPâJ¿µ@ŽË ?
?–The meanings of the three-letter abbreviations are as follows:
?ƒÌ+
+–Here is the layout of the status register:
+÷Í3D—Ü
––
––P–$–%–&–P0–<–=–>–PH–T–U–V–P`–l–m–n–Px–‹–’–“–P–º–»–¼–PÆ–Ó–Ô–Õ–Pß–ì–í–î–Pø––––P––– –P*–>–E–F–P`–t–~– bit 0 IVO flag
bit 1 DVZ flag
bit 2 OFL flag
bit 3 UFL flag
bit 4 INX flag
bits 5 to 15 Unused (These are read as zero)
bit 16 IVO mask
bit 17 DVZ mask
bit 18 OFL mask
bit 19 UFL mask
bit 20 INX mask
bits 21 to 23 Unused (These are read as zero)
bits 24 to 31 System id (These are 'read-only')
§ªª©¨5\¯²²±°6\7UÏ‹
‚ª –System id - These eight bits may be used to determine which type of FPU the system is running. The only one currently defined is bit 31:
Mß>jÁ%Ñ
º–®–The versions with the E suffix generate an exception if the operands are 'unordered' (when at least one operand is a NAN) and thus can't be compared. After the instructions, the ARM flags are set as follows:
IÄC§E£Â·@
%–®–@-–4®5–@V–]®^–@Š–‘®’– N set if 'less than' else clear
Z set if 'equal' else clear
C set if 'greater or equal' else clear
V set if 'unordered' else clear
-Ð)»4þ-ÛÃ,ùd
–}®–®ƒ–…®‡–‹®–® –¥®¨–Í®Ï–Ñ®Ó–é®í–ò®ö–According to the IEEE standard, when testing for equality or for unorderedness, where the next instruction condition will be EQ, NE, VS or VC you should use CMF (or CNF). To test for other relationships (GT, LE etc.) you should use CMFE (or CNFE).
A’JÎOßÈÄ
^8
–@®
–@® –$®6–@7–;®>–where:
is R0-R14
is #{+|-}
and {!} specifies optional write-back.
Çw(
–@®–@®–@Y–where:
x means 'don't care'
s means 1 for negative, 0 for positive (number, zero or INF)
Maximum is 255 (for NANs etc)
,=uÆÀ<‡
‡–In describing the FPU's instruction set, we have to use certain terms which are specific to floating point arithmetic. These are explained briefly in this section. For a more detailed discussion, you should see the appropriate IEEE standard document (ANSI/IEEE 754-1985) , or manufacturer's data on one of the current available FPUs (e.g. the Motorola MC68881 or Western Digital WE32206).
LÒPÒIÀHÞHÓqÁ ´
´–If the interrupt for the error condition is disabled, the status flag still gets set, but execution of the program is not affected. A special result, e.g. NAN or INF is returned.
QÊO×vÂCel
@–P–PL–Pe–Pu–z®}–“®––@™–š®–@¤–PÚ–Û®Þ–æ®é–@ð–ñ®ô–@
–P%– Any operation on a NAN
Trying to 'cancel' infinities, e.g. -INF plus +INF
Zero times +INF or -INF
0/0 or INF/INF
INF REM anything or anything REM 0
SQT( <0 )
Converting INF, NAN or too large a number to integer
ACS( >1 ), ASN( >1 )
SIN(INF),COS(INF), TAN(INF)
LOG( <=0 ), LGN( <=0 )
Writing to the unused or system id bits of the status register
t·4F¸~$W6u™éµ@ŽÃ'Ó
Ðª–DVZ - Divide by zero. This is caused by trying to divide a non-zero number by zero. The result, if the error is not trapped, is an infinity of the appropriate sign (e.g. -1/0 gives -INF, -32.5/-0 gives +INF).
LÖI™>wÄ*ë
ë–Obviously you cannot have fractional numbers of significant digits, so the values should be truncated to 7, 15 and 19 respectively. The fractional part means that one extra digit can be stored, but this cannot go all the way up to 9.
KÎNÔOÞÅ7F
F–Just because a number can be represented exactly in decimal, do not assume that its binary representation is also exact. For example, the decimal fraction 0.1 is actually a recurring fraction in binary, and can never be stored exactly (though of course, when enough digits are used in the mantissa, the error is very small).
KÙH²QßLØzÆDŸ(
9–F–Œ–Ô––f–The table shows how many bits the exponent uses, and the smallest and largest factors by which the mantissa may be multiplied. The formula n*0.3010 can also be used to find out what power of ten these exponents correspond to. They are +/-39, +/-307 and +/-4931 respectively. Thus a single precision IEEE number could represent the number 1.234E12 but not 1.234E45. This would require a double precision number.
eFÁFµHÄIÃIÑ9bÇ>S
S–The exponent is held in an excess-n format, as with BBC BASIC. The excess number is 127, 1023 and 16383 for the three precisions respectively. Note that there is an exponent value at each end of the range (e.g. -127 and +128, stored as 0 and 255, in single precision) which is not used. These values are used to represent special numbers.
JÛOáI¾NÒ#×È®
®–These four modes can be illustrated by using decimal numbers. Suppose that the calculations are performed to nine digits precision, and the final precision is seven digits:
LàG©—É50
*ª–IVO - Invalid operation. There are several operations which are deemed 'invalid', and each of these sets the IVO flag, and causes the instruction to be trapped if enabled. If the trap is not enabled, an operation which causes the IVO flag to be set returns NAN as the result. Invalid operations are:
HËQßOÛHÊ:2
2–where >1 means 'a number greater than one' etc, and INF means either +INF or -INF. Note that in the case of converting an INF or too large a number to an integer, the result (if the error is not trapped) is the largest integer of the appropriate sign which can be represented in 32 bits two's complement.
EÂIÄNÅJÃQËZã0
E®
–®–ª®–›®ž– and are the ARM register to or from which the 32-bit FPU status register is transferred. The format of this register is described above. After an RFS the ARM register will contain the state of the status flags and interrupt masks. The unused bits will be set to zero, and the system id part will be as described above. A program can clear the flags and set the desired mask bits using WFS. Zeros should be placed in the unused bits and the system id bits.
DàK·NßPÝNÜKÊ¢Ì—
—–The format of this register is system dependent. These are privileged instructions and will abort if an attempt is made to execute them in user mode.
G²JÂ'ÍE
E–where all terms are as described in section B.3. The mnemonics are:
E¦À
šš
ÿ¹Þ Þ!Ø.P ‚ Ž¡–z¡šÿý ˜
.P
++&Sign ™ —¡–z¡šÿý ˜)%Exponent ™ —¡–z¡šÿýS ˜)Hmsb Mantissa lsb ™ —0(,G0F,0Ž,C¡–z¡šÿý
˜(/31 ™ —¡–z¡šÿý
˜)30 ™ —¡–z¡šÿý
˜)623 ™ —¡–z¡šÿý
˜)22 ™ —¡–z¡šÿý ˜)«0 ™ —"X$ 9¡–z¡šÿý ˜(bit: ™ — ƒÿÁ‡
'–@"–@O–@`–Exponent = 11 bits, excess-1023.
Mantissa = 52 bits, implied 1. before bit 19
Formats as above
Maximum exponent (for NANs etc) = 2047
"Ë-p'
»¬ ¬!¦Eˆ ‚ Ž¡–¡šÿý ˜
Eˆ
+c&Sign ™ —¡–¡šÿý ˜)%Exponent ™ —¡–¡šÿýS ˜)Hmsb Mantissa lsb ™ —0`,0~,Ç0Æ,{¡–¡šÿý
˜(g31 ™ —¡–¡šÿý
˜)30 ™ —¡–¡šÿý
˜)620 ™ —¡–¡šÿý
˜)19 ™ —¡–¡šÿý ˜)«0 ™ —"$ Øq¡–¡šÿý ˜(Cbit: ™ —¡–¡šÿý" ˜(&
First Word ™ —00`C{¡–¡šÿý‰ ˜+Y"msb mantissa )ª lsb ™ —¡–¡šÿý* ˜(<Second Word ™ — ƒÿ¼ý ý!÷^Œ ‚ Ž¡–¡šÿý ˜
^Œ
+g&Sign ™ —¡–¡šÿý ˜)%Exponent ™ —0d,ƒ0‚,Ë0Ê,¡–¡šÿý
˜(k31 ™ —¡–¡šÿý
˜)30 ™ —¡–¡šÿý
˜)616 ™ —¡–¡šÿý
˜)15 ™ —¡–¡šÿý ˜)«0 ™ —"”$ Üu¡–¡šÿý ˜(Gbit: ™ —¡–¡šÿý ˜+¶Zeros ™ —¡–¡šÿý" ˜(%
First Word ™ —01dD01dDƒ¡–¡šÿý ˜+dJ ™ —¡–¡šÿý* ˜(<Second Word ™ —¡–¡šÿý‹ ˜+^"msb mantissa )ª lsb ™ —0Id\¡–¡šÿý% ˜(T
Third Word ™ — ƒÿÄ\
(–@!–@4–Exponent = 15 bits, excess-16383
Mantissa = 64 bits
Maximum exponent (for NANs etc) = 32767
!Ër(¾¥ ¥!Ÿc` ‚ Ž¡–¡šÿý" ˜
c`
+(
First Word ™ — Ž0e/„0ƒ/¢0¡/À0¿/Þ0Ý/ü0/807/V0û/ ¡–¡šÿý ˜+[Sign ™ —¡–¡šÿý ˜)$e3 ™ —¡–¡šÿý ˜)e2 ™ —¡–¡šÿý ˜) e1 ™ —¡–¡šÿý ˜)e0 ™ —¡–¡šÿý ˜)d18 ™ —¡–¡šÿý ˜)d17 ™ —¡–¡šÿý ˜)d16 ™ —¡–¡šÿý* ˜(@Second Word ™ — Ž Ž05eH„05ƒH¢05¡HÀ05¿HÞ05ÝHü05H8057HV05ûH ¡–¡šÿý ˜+[d15 ™ —¡–¡šÿý ˜) d14 ™ —¡–¡šÿý ˜)d13 ™ —¡–¡šÿý ˜)d12 ™ —¡–¡šÿý ˜)d11 ™ —¡–¡šÿý ˜)d10 ™ —¡–¡šÿý
˜)!d9 ™ —¡–¡šÿý
˜)d8 ™ — ¡–¡šÿý% ˜(Y
Third Word ™ —0Nea„¡–¡šÿý
˜+`d7 ™ —0Nƒa¢¡–¡šÿý
˜)d6 ™ —0N7aV¡–¡šÿý
˜)´d0 ™ —0N¡aÀ¡–¡šÿý
˜([§d5 ™ —0N¿aÞ¡–¡šÿý
˜)d4 ™ —0NÝaü¡–¡šÿý
˜)d3 ™ —0Nûa¡–¡šÿý
˜)d2 ™ —0Na8¡–¡šÿý
˜)d1 ™ —¡–¡šÿý
˜(j31 ™ —¡–¡šÿý ˜+à0 ™ — {I ƒÿÆ'½$
5–@–@6–@U–@ˆ–Each field is four bits
e0-e3 are the exponent digits
d0-d18 are the mantissa digits
Bit 31 of the first word is the sign of the number
Bit 30 of the first word is the sign of the exponent
(‚µ¼3'52¿¸ÞF‹ÿóÿÿÿÿ€º@Š‰ÿóÿÿÿÿ€»~°ÿòÿÿÿÿ€½œ¸ÿòÿÿÿÿ€ÁP
.–@"–Exponent = eight bits, excess-127
Mantissa = 23 bits, implicit 1. before bit 22
À
¿
¼HH
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